1. Field of the Invention
The present invention generally relates to metal-oxide-semiconductor field-effect transistors (MOSFETs), and more specifically to a method of fabricating a MOSFET or other semiconductor device including a structure for suppressing punchthrough using symmetrical high tilt angle implants.
2. Description of the Related Art
Advances in integrated circuit technology have made possible the fabrication of MOSFETs with channel lengths of less than one-half micrometer. In order to prevent punchthrough, in which the depletion regions of the source and drain merge together to form an uncontrollable continuous channel, the doping of the substrate in the channel region is conventionally made considerably higher than in MOSFETs with longer channels. However, this produces a steep doping concentration gradient across the source/substrate and drain/substrate metallurgical junctions, which increases the electric fields across the junctions and creates undesirable effects including snapback and gate oxide charging.
FIG. 1 illustrates a P-channel, enhancement mode MOSFET 10 which is provided with a conventional arrangement for suppressing punchthrough. The MOSFET 10 comprises a silicon substrate 12 which is lightly doped N-type. A source 14 and a drain 16 which are both heavily doped P-type are formed on opposite sides of a channel 18. Metal contacts (not shown) provide external connection to the source 14 and drain 16.
A gate oxide layer 20 is formed over the channel 18, and a conductive polysilicon layer 22 which constitutes a gate electrode is formed over the gate oxide layer 20. Further illustrated are oxide spacers 24 and 26 formed on the opposite sides of the polysilicon layer 22.
Regions 28 and 30 which are lightly doped P-type are formed between the source 14 and the channel 18, and between the drain 16 and the channel 18 respectively. The regions 28 and 30 provide a "lightly doped drain" structure in the form of a reduced dopant concentration gradient that reduces the electric field across the drain/substrate and source/substrate metallurgical junctions and thereby suppresses punchthrough and related effects.
The MOSFET 10 further, as disclosed in U.S. Pat. No. 5,147,811, entitled "METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY CONTROLLING THE PROFILE OF THE DENSITY OF P-TYPE IMPURITIES IN THE SOURCE/DRAIN REGIONS", issued Sept. 15, 1992 to E. Sakagami et al, comprises lightly doped N-type pockets or electric field containment regions 32 and 34 formed under the source 14 and drain respectively.
The regions 32 and 34 extend around the ends of the source 14 and drain 16 respectively toward the surface of the channel 18, and partially absorb and thereby contain the electric fields that cause depletion regions to expand from the source 14 and drain 16 toward each other through the channel 18. This electric field and depletion region containment arrangement suppress punchthrough.
The regions 32 and 34 are formed as disclosed in the above referenced patent to Sakagami by ion implantation at an angle that is tilted from a normal to the surface of the substrate 12. The tilt angle is made small, on the order of 8.degree., in order to minimize "channeling". Generally, if ion implantation is performed at an angle that is parallel to a crystallographic axis of the substrate 12, the ions will penetrate more deeply than desired or "channel" into the substrate 12. The channeling effect tends to increase as the tilt angle is increased.
Although effective, the punchthrough suppression arrangement including the regions 32 and 34 is disadvantageous in a large scale integrated circuit in which MOSFETs are arranged such that the channels of some of the MOSFETs extend perpendicular to the channels of others. For this reason, the punchthrough implants for the two different MOSFET orientations are conventionally performed separately.
More specifically, the implants for the MOSFETs of one orientation are performed from two opposite angles, and those for the MOSFETs of the other orientation are performed from two opposite angles that are perpendicular to the first two opposite angles. Although producing the required result, the operation is extremely time consuming since the substrate must be selectively rotated by 90.degree. for implanting each MOSFET.
The patent to Sakagami teaches how to perform punchthrough implants in one continuous operation by rotating the substrate during implantation. This produces a continuous implant region having a generally cup shape under each MOSFET. The implant region is not, however symmetrical since the channeling effect varies with the crystallographic orientation of the substrate. This asymmetry has a substantial and undesirable effect on the electrical properties of the MOSFETs.
Another expedient is to form a punchthrough implant in the form of a flat, continuous layer under each MOSFET. This method, however, suffers from difficulty in controlling the electrical properties of the MOSFETs that result from the implant, and undesirably increasing the threshold voltages of the MOSFETs.